The electrical current required to maintain data integrity in static random-access memories (SRAMs) has dramatically increased as the cell size has been reduced. The dominant leakage mechanisms in a modern complementary metal-oxide-semiconductor (CMOS) six-transistor (6T) SRAM cell are transistor gate leakage and sub-threshold leakage. In the last several years, gate leakage has been controlled to some extent through the use of high-dielectric-constant (HIGH-K) metal gates. Sub-threshold leakage, on the other hand, is still a challenge for low power SRAMs.